Under the current situation where systems have become complicated and the multicore configuration equipped with a plurality of processors (CPUs for example) has become common, the realization of a higher processing speed and processing accuracy has been required for the simulation process of the function, performance, power and the like of each core (CPU).
In the simulation of the function, performance, power consumption, in the case of making the target CPU being the evaluation target on the host CPU, the adoption of the interpreter system or the JIT (Just-in-Time) complier system as the conversion method from the instruction code (target code) of the target CPU to the instruction code (host code) of the host CPU code has been known.
In the simulation in the JIT complier system, for the target CPU being the simulation target, the instruction of the target CPU that appear in the program being executed is replaced with the instruction of the host CPU that executes the simulation, and after that, the replaced instruction is executed. Therefore, the process in the JIT complier system is faster compared with the process in the interpreter system, and in the function simulation of the CPU, the JIT compile system has been adopted especially when the high speed is required.
The performance simulation of the CPU adopting the JIT complier system has also been proposed.
However, in the control of the pipeline process in which the respective units are made to operate independently for each clock and instructions are input one after another and executed in parallel, the internal condition of the CPU changes every time when the process is executed, an advantage of the JIT complier that a host instruction is used repeatedly once it is generated.
Therefore, generally, it has been regarded that the JIT complier method is not suitable for the performance simulation and the power simulation for the CPU that controls the pipeline process and the out-of-order process.